Zen 4 Epyc: Image of a 96-core Genoa and a scheme of a 128-core Bergamo chiplet (?)

Epycu’s shot Genoa you see in the introduction. It is a new socket (SP5), which is larger and more square to fit more chipsets in the case. As we already know, he has them in the case Genoa be twelve of eight cores, ie 96 cores in total. Processor chiplets will be 5nm, central according to some sources 6nm.

The photo essentially confirms AMD’s claim last year that partners are already receiving samples Genoa and nothing prevents the expected release in 2022, ie this year.


In addition to this photograph, another image appeared, which also relates to architecture Zen 4 and which was published by the editors of the WCCFTech website with the words that it is a chiplet Zen 4 from desktop processors Raphael:

If this scheme shows the real product at all (which is of course possible and we will assume that yes – let’s omit the typo “V-Cahce”), then it is difficult to show the desktop Raphael. What we actually see in the picture: This is a chiplet that carries a total of 16 Zen 4 cores. The chiplet lacks the L3 cache, it contains only the L2 cache. The L3 cache is layered on eight central cores. To satisfy heat dissipation, CPU cores are used as follows: When a lower number of cores is loaded (when these cores run on a high boost and each generates a higher amount of waste heat), the cores at the edges of the chip that are not covered by the cache are used. Only when the eight regional cores are depleted are the central cores used.

Processor core consumption depending on the number of loaded cores (Ryzen 9 5950X, according to Anandtech)

Due to the limitation of TDP, a lower frequency is achieved when all cores are loaded, and the waste heat generated by individual cores is many times lower (for an idea of ​​this dependence, see the table above). So it makes quite a sense, such a solution may work well.

Now to what hardware actually captures the image. Raphael hard. According to current information, it is supposed to have 16 cores, with the possibility of producing a 24-core version being considered. The 24-core processor will probably not consist of 16-core chipsets. We also know that the 96-core Epyc Genoa should have 12 chipsets, so they are chips with eight cores. In the end, the 30W limit on the covered core would give 240 watts when adding (30 × 8), which really has nothing to do with a classic desktop (240 watts is also a value without counting core cores, which have no 30W limit).

However, we know that there should be a product that specializes in the maximum number of cores, should have a dug-through cache structure, and can expect a TDP in the hundreds of watts. What is it? 128-core Epyc Bergamo. This is what is known to focus on compacting the number of cores per unit area and maximizing energy efficiency (ie dizzying cycles). The diagram shows a chiplet where, by omitting the L3 cache, space was freed for other cores, the number of which was doubled, while the L3 cache was moved completely to a separate layer. It is worth noting that although the capacity of both the L3 cache and the L2 cache per kernel remains the same as in the current models, the structure of the L2 cache has changed. In the current Zen each kernel has its own 0.5 MB of this cache. 1 MB for two cores is used here. This is a similar offset as with the L3 cache between Zen 2 a Zen 3when the former had separate 16 MB for 4 cores, while the latter 32 MB common for 8 cores. This can hold a larger block of data at the same time and does not need to be moved if the other kernel needs data from one part of the cache.

Although it is not possible to say with 100% certainty that the picture shows the diagram of the Epyc chiplet Bergamo, I dare say that if the diagram shows a real product, it is Bergamo. What the diagram shows and what we know (and expect) from Bergama it fits together well.


Source: Diit.cz by diit.cz.

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