The Playstation 5 L3 cache is apparently shared for both CPU and GPU

When RDNA 2 and Infinity Cache graphics architecture was introduced, information emerged from one of AMD’s engineers that although the technology was introduced on a high-end product, its idea was not initially aimed at high-end, but at mobile graphics chips and APUs. . For mobile GPUs, the pressure is on the narrowest possible bus (there is no space for a large PCB) and low power consumption (which is helped by the large integrated cache). For an APU, it can then address a barrier that reduces the sense of integrating more powerful GPUs: Limiting the performance of memory bus throughput to RAM.

However, as the long-term care of Internet leakers soon showed, AMD does not plan to integrate Infinity Cache into the APU as we know it from standalone graphics, but rather it looks like SLC, System Level Cache, which is the highest level cache shared for CPU and GPU. The GPU will appreciate such a cache the most, but once it is present, why can’t it be used by processor cores? Some percentage of the performance it can give. And not only that.

However, it seems that the implementation of such a solution in PC APU will not be a premiere for AMD. Following the release of detailed images of the Playstation 5 game console core by photographer Fritzchens Fritz, several people became convinced that such a solution was already used by Sony game consoles.

Interestingly, the L3 cache of Playstation 3 is not large, it reaches a capacity of 8 MB. Since last November, it is known that although it connects the nuclei Zen 2, is monolithic, which in PC came up with architecture Zen 3. However, it seems that not only does it surpass the technological level of the second generation Zenu. If it is really the so-called system and serves not only processor processors but also graphics cores, then the question arises, what makes sense at 8MB capacity. For a PC APU that is limited to a (maximum) 128bit DDR4 bus, such an effective data throughput solution would also help, but for a console with a 256bit GDDR6 bus, this cannot have a significant effect. It seems that in this implementation, the primary goal did not have to be data throughput or consumption, but a possible effort to share data more efficiently between processor and graphics cores. In the end, such a bonus could also be advantageous from the point of view of the PC.

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