At the beginning of the year, the head of Intel’s graphics division, Raja Koduri, boasted of the Ponte Vecchio accelerator. In March, Koduri (also Intel CEO Pat Gelsinger) revealed further details. Among others, they published a photograph of a water-cooled laboratory sample. The use of hydrogen in samples under development is not unusual and does not in itself mean that such cooling will be used in mass-produced pieces.
As Igor Wallossek found out, in the case of Ponte Vecchio, however, the accelerator waterman will remain. The documentation page (introductory image) describes the attachment of the OAM (ie the module; the accelerator will therefore be implemented in the form of an OAM, not as a PCIe card or socket solution) and the attachment of the water cooler to the module. According to Wallossk, it is possible that the consumption of the module will slightly exceed 600 watts, which is not surprising given the total area of silicon.
Ponte Vecchio consists of more than 100 billion transistors distributed between 47 chips (chips) and, apart from Intel’s somewhat pathetic terminology, calls these tiles “magical” and the “alchemy” interconnection system, it is a very technologically interesting solution. Intel connects the individual tiles using bridges, or (it seems) to a limited extent also with interposers. Only 42 tiles out of a total of 47 listed by Intel are visible on the case itself, so the other 5 can function as an interposer (Intel bridges do not include up to 47).
The case carries tiles manufactured by the 7nm and 5nm TSMC process and the 10nm and 7nm Intel process. Given the not entirely favorable news on the status of Intel’s 7nm process, Intel cannot be expected to produce more of these accelerators in the near future than will be needed to cover the order for the Aurora supercomputer. At least, provided that the mass-produced version will use Intel’s 7nm process for one of the chipsets.
Source: Diit.cz by diit.cz.
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