The first 2-nanometer circuit has been completed at IBM

IBM’s development can accommodate roughly 333.33 million transistors per square millimeter, a value nearly 96 percent higher than the 5-nanometer TSMC process in mass production since last year. In short, this means that nearly twice as many transistors can be placed in a unit area, which can significantly reduce the chip area or double the critical value with an unchanged area.

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IBM compares 2 nanometers to its own 7-nanometer process, which offers up to 45 percent higher transistor densities or 75 percent lower dissipation in this regard. The fair value will depend on which feature engineers prefer when designing. In the case of battery-powered products, the latter, i.e. lower dissipation, is generally preferred, but at the same time, higher performance does not have to be waived, depending on the goals set by the respective chip design.

IBM’s development uses new transistors in addition to the increasingly widely used EUV, i.e., ultraviolet light. Like its competitors, the development lab is building its 2-nanometer process on GAA (Gate-All-Around), also known as a nanowire / nano-plate transistor, which has somewhat more favorable electrical properties than FinFET while significantly improving scalability.

An interesting addition is that IBM has for some time been producing only test chips that are essential for development work. Big Blue sold its plant to GlobalFoundries back in 2014, meaning it has been slowly engaged in mass production for seven years. However, the research and development center has survived and, according to the report, serious work is underway in a laboratory in the city of Albany. IBM is working with Samsung and, more recently, Intel, among others, on the future processes of the two manufacturers, so there is a good chance that the development just announced will return in some future products of the two major players.

Source: HWSW Informatikai Hírmagazin by

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