The Performance series was immediately knocked out by Intel, so they can also release their own production capacity to licensors.
Back in mid-2016, SiFive announced the launch of the industry’s first open source chip design platform, which sees the RISC-V architecture as its foundation. Since then, many designs have been available to customers, but the palette lacks the really high-performance cores, but the new Performance series eliminates this unfortunate condition.
The company is planning two new cores labeled P270 and P550. What they have in common is that they fully meet the needs of Linux and use a 64-bit RISC-V instruction architecture.
The P270 is a less powerful and specialized design, with the RISC-V Vector Extension v1.0RC instruction set, which also features a 256-bit vector processor. The system itself, on the other hand, uses in-order logic, meaning that incoming tasks can be processed in order, and a configuration equipped with an eight-stage conveyor belt and private L1 and L2 caches can load two instructions per clock cycle.
The P550 uses a somewhat more general core, including OOO logic, meaning incoming tasks can not only be processed in order, its conveyor has grown to 13 steps, and it can load three instructions per clock cycle, but we have to give up the RISC-V Vector Extension v1.0RC instruction set.
According to the company, the P270 is capable of scoring 4.6 points per gigahertz in the SPEC2006 int test, compared to 8.65 points per P550 design. The latter value is otherwise very good, especially since four SiFive P550s can be built in place of an ARM Cortex-A75 core, while the chip space used is similar. The company has designed the entire Performance series for scalability, a processor cluster can contain four cores that use a common L3 cache, and the addition of additional clusters makes it possible to incorporate even more cores.
SiFive will, of course, continue to work with leading contract manufacturers, and alongside Samsung and TSMC, Intel will also be lining up for their 7-nanometer node. The Santa Clara-based company specifically licenses SiFive’s IP portfolio, which the company’s prospective partners can access on their upcoming manufacturing technologies.
This is a very important step for Intel, as they need more than anything to have customers for the 7-nanometer node, meaning that they are not just bearing the financial burden of manufacturing technology changes, which is becoming increasingly difficult to manage. They are also planning a development platform for RISC-V called Horse Creek, which will use four P550 cores that share a 4MB L3 cache. The latter is mostly a forward-looking concept that could serve the faster spread of RISC-V.
Source: Hírek és cikkek – PROHARDVER! by prohardver.hu.
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