Although it may be worth noting that last year some manufacturers convinced us that there is no need for more than seven years old PCIe 3.0, by the end of this year PCIe 4.0 should be “totally out” and in a while we will probably hear the same about PCIe 5.0 , as PCIe 6.0 moved to version 0.9, the so-called Final Draft.
What this means: During the development of a new generation interface, the design goes through several phases that have experienced designations. Version 1.0 is considered the final specification, so 0.9 is the last point before closing it:
- 0.3 – Concept (2019)
- 0.5 – First Draft (únor 2020)
- 0.7 – Complete Draft (July 2020)
- 0.9 – Final Draft (October 2021)
- 1.0 – final specification
As expected, PCIe 6.0 delivers transmissions of up to 64 GT / s per line (ie 8 GB / s per line, ie 128 GB / s for × 16 lines), PAM4 support (= Pulse-amplitude modulation, which allows transmission instead of two states states of four (00, 01, 10, 11), so the baud rate doubles at the same clock frequency, but because the resolution of four states is more difficult than the resolution of two states, the signal purity demands increase and the necessary condition of Forward Error Correction increases. As a “bonus” for the deployment of PAM4, extra silicon is provided to maintain backward compatibility with the original NRZ coding.
Therefore, PAM4 support will not be “free” (it will require extra silicon), and higher absolute energy requirements can be expected. Therefore, it is possible that the PCIe 6.0 standard will not penetrate mainstream computers as fast as previous generations. The consensus expectation is that PCIe 6.0 will start first in the professional segment, where the cost of its support is easier to pay, while in the personal computer segment, where there is a margin in the form of PCIe 4.0 and PCIe 5.0, it will appear later.
Source: Diit.cz by diit.cz.
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