PCI-SIG releases the PCIe 6.0 specification

PCI-SIG, the organization responsible for the development of PCIe standards, has officially announced the release of the PCIe 6.0 specification.

This new breakthrough in PCIe technology will deliver double the power efficiency and bandwidth of the previous PCIe 5.0 specification (capable of “only” 32 GT / s) and still provide lower latency levels with reduced overhead problems. to a minimum.

That bandwidth translates to approximately 16GB / s per PCIe 6.0 line, which is 256GB / s (bi-directional) for a full size x16 slot.

The drastic leap in performance over PCIe 5.0 comes as no surprise as each new generation of PCIe doubles the bandwidth of the previous one.

These results are obtained thanks to the introduction of Pulse Amplitude Modulation technology with four-level coding (PAM-4), which replaces the current Non-Return-to-Zero (NRZ) on two levels thanks to the implementation of a error correction technique (FEC) to preserve data integrity and a Flit-based coding (flow control unit).

PCI-SIG has adopted a 256-byte Flit structure, including variable-sized Transaction Layer Packets (TLPs) and Data Link Layer Payloads (DLLPs).

The PCIe 6.0 specification will offer initial support only for markets that require heavy data transfer such as data centers, artificial intelligence and machine learning, HPC, automotive, IoT and military aerospace,

For more information, please visit the consortium website directly PCI-SIG.


Source: Nexthardware All by www.nexthardware.com.

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