Navi 31: 4 TB/s k Infinity Cache a 1 TB/s k GDDR6

Some leaks expect the Navi 31 to look roughly as shown in the diagram below. In the middle (red) GCD, ie 5nm chiplet with computing blocks (in this sense also PCIe, front-end, multimedia, video outputs, etc.) and around the GCD there are six 6nm chiplets integrating the memory interface (64bit block in each) and Infinity Cache . The chips are interconnected by a 65nm wafer. No longer a classic silicon interposer limited by chip dimensions (so-called reticle limit, max. Approx. 860 mm²), but a part of the wafer that can be illuminated twice (the reticle limit is therefore doubled, approx. 1700 mm²).

Alleged form of Navi 31; source: AMDGPU

Data throughput between GCD and MCD (connected via CoWoS) should reach 4 TB / s. Each MCD should carry 64 MB of SRAM (Infinity Cache), which would correspond to a total of 384 MB. It should be noted that there are mentions of 192 MB and you can still come across the data of 256 MB (even this is technologically feasible, in which case it would be 48 MB of SRAm on the MCD).

The basic question is what it will be like Navi 31 effective memory throughput available. The physical throughput of the memory bus is clear: 384 bits in combination with GDDR6 means (according to specific chips – 16-18-21GHz) 768-864-1008 GB / s. It is not certain what chips AMD will install, the leaks differ. There are probably samples with different memories. It will be more important how much Infinity Cache adds to the effective memory throughput.

hit-rate and effective IC throughput (GB / s)
8 MB124 GB / s5 mm²25 %3117 %2114 %17
12 MB186 GB / s7 mm²31 %5819 %3515 %28
16 MB248 GB / s10 mm²37 %9225 %6217 %42
24 MB373 GB / s15 mm²48 %17931 %11624 %90
32 MB497 GB / s20 mm²55 %27339 %19426 %129
48 MB745 GB / s29 mm²66 %49249 %36534 %253
64 MB993 GB / s39 mm²72 %71559 %58641 %407
96 MB1490 GB / s59 mm²78 %116266 %98352 %775
128MB1987 GB / s79 mm²81 %160974 %147062 %1232

To calculate some result, we can start with the table I prepared last year based on a slide with the AMD chart, which expressed the dependence of the hit-rate on the resolution and capacity of the Infinity Cache as it was used on RDNA 2.

By extrapolation, we find that using the 192MB Infinity Cache, the hit rate would reach about 67% and at 384MB capacity about 78%. I take 4K resolution into account. If the data throughput of the Infinity Cache chiplet is to be a total of 4096 GB / s, then at a hit rate of 67% it would provide about 2744 GB / s and at a 78% hit rate of approximately 3195 GB / s.

effective data throughput (GDDR6 + IC)192MB IC
(2744 GB / s)
256MB IC
(3072 GB / s)
384MB IC
(3195 GB / s)
16Gb/s GDDR6 @384bit (768 GB/s)3512 GB / s3840 GB / s3963 GB / s
18Gb/s GDDR6 @384bit (864 GB/s)3608 GB / s3936 GB / s4059 GB / s
21Gb/s GDDR6 @384bit (1008 GB/s)3752 GB / s4080 GB / s4203 GB / s

Thus, the effective data throughput would be around 3.5-4.2 TB / s. Recall that the Radeon RX 6900 XT (Navi 21) had 512 GB / s (GDDR6) + effective throughput (4K) Infinity Cache 1152 GB / s, a total of 1664 GB / s efficiently. If the goal Navi 31 was 2.5 times higher performance (× Radeon RX 6900 XT), then taking into account the overall lower demands of the architecture for data throughput (improved delta-compression support) and 384bit bus, a combination of basic 16GHz GDDR6 with 192MB Infinity Cache capacity (ie 3512 GB / s effectively total). The 384MB variant thus seems practically a waste (when we move in such high capacities, doubling the capacity means only a 12-13% increase in effective data throughput).

Although most sources currently talk about 384 MB, I personally see no reason why a chip would not be enough with 192 MB (6 × 32 MB) or 256 MB (6 × 48 MB).

Source: by

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