Intel Xeon Sapphire Rapids postponed again, instead of spring it looks like September

Designation Sapphire Rapids we have been hearing for at least three years. The first mentions of it were a bit inaccurately interpreted and assumed that it was Intel’s new x86 architecture, which was attributed to some major intergenerational shift (some believed that it was a processor developed by Jim Keller during his time at Intel). As it turned out later, neither is true – Sapphire Rapids from the beginning referred to a server processor (Xeon) built on x86 cores Golden Cove, that is, the same large cores that PC processors use Alder Lake / Core 12000.

In May 2019, the official and Intel-published roadmap was made public for the first time Sapphire Rapids discovered. It was painted for 2021. At the same time, a more detailed partner roadmap appeared, according to which it had Sapphire Rapids come out at the very beginning of 2021, ie (from the current point of view) a year ago:

Intel believed this (or at least claimed it) at the turn of 2019/2020, when Intel’s chief engineering officer, Venkata Murthy Renduchintal (in the introductory picture), stated:

Intel will ship the Whitley platform as planned by Cooper Lake in the first half of 2020, followed by Ice Lake in the second half of 2020. We also continue as planned with Whitley’s successor with Sapphire Rapids deliveries in 2021.

— Intel’s chief engineering officer, Venkata Murthy Renduchintala, December 2019

However, the statement was cautious, as the word “supplies” may not include any release.

In any case, shortly afterwards, it was rumored that it would not go so smoothly, and reports of delays followed. Over time, the beginning of 2021 became the beginning of 2022, in the second half of last year, there was talk of the second quarter of 2022, and more and more it looked more like its end. In the first half of 2021, however, it seemed that in the second quarter there would be a server Sapphire Rapidsso that the third could (after a very long time) be followed by HEDT, an ultra high-end desktop and some workstation.

Xeon Sapphire Rapids ve verzi s HBM

But it probably won’t work out that way either. Dolly Wu, vice president and CEO of Inspur Systems, the world’s second-largest server maker, was released. According to Wu, there was a postponement Sapphire Rapids for the third quarter, not its beginning, but its end. Deliveries from series production are scheduled to start in September.

Dolly Wu, Vice President and CEO of Inspur Systems

Such a slippage has several effects:

  • Sapphire Rapids will not actually compete with AMD Epyci-based architecture Zen 3; years Milan, years Milan-X (V-cache models). Epyce with cores is expected to be released by the end of the year Zen 4 (Genoa) whose actual competitor is Sapphire Rapids stands.
  • Because he was Sapphire Rapids designed as a competitor for Epyc Milan (or maybe the other way around – Milan as a competitor for Sapphire Rapids, which is basically the same) – one has a 12-15% higher IPC, the other a 14% higher number of cores – has no general chance to succeed compared to the Epyci Genoa, which will bring up to 25% IPC shift (min. 12% compared Golden Cove), up to 50% shift in the number of cores and higher energy efficiency due to the 5nm process.
  • AMD’s share of the server processor market is unlikely to be just a downturn, but in the absence of competition to Epycem Milan for the next three quarters, AMD’s share will not decline.

However, this is also a “problem” for AMD, which apparently did not expect to be on the market alone for such a long time, even in the most optimistic outlook. It does not currently have production capacity to take over another part of the server market. In addition, TSMC increased the price of the 7nm process throughout last year, so instead of falling production costs over time and yield, they are rising. The company allegedly decided to solve this by not concluding long-term contracts with customers and informing them about delivery volumes, but with the realization of each batch it will offer them goods at prices 10-30% higher than last year and give server manufacturers a choice whether to take goods. or not. According to Ms. Wu from Inspuru, none of the customers has declined the offer yet.

For AMD, however, this means that although its current generation of server products is virtually unrivaled, it does not currently have production volumes that allow the situation to take advantage of and further increase market share. Wu estimates that in 2021, AMD achieved a roughly 20-25% share in servers (as we know, different companies define the scope of the server market differently, so the number may not be comparable with data from other sources) and assumes that in 2022 it will be AMD share similar.

At the end of the year, it will issue 5nm Epycy (the use of 5nm lines will give it some space to expand production capacity), but at that time it will Sapphire Rapids on the market (which bites some of the cake) and on the one hand, the last month or two no longer have a chance to have a significant impact on the annual statistics.

Finally, we can ask ourselves what could have led to another such significant delay. We know that Sapphire Rapids based on architecture Golden Cove, which has been on the desktop since last fall. We know that it uses the Intel 7 process, which has also been used on the desktop since last autumn. Moreover, it is not a gigantic monolith, with which the yield would have to be completely per… fruiting body of macromycetes.

Despite this, there are some problems. These may be issues that exist at the architecture level (but the PC version doesn’t matter, while the server version, where ECC, security and AVX-512 are advanced for Intel, yes), but it can also be the specifics of encapsulation. For Intel it is Sapphire Rapids the first tiled Xeon.

However, in the context of AMD nomenclature, we would use the term “modular” rather than “chiplet”. Sapphire Rapids consists of four basic pieces of silicon that are identical, symmetrical (and roughly square). Each carries up to 14 active cores (how many of them it contains physically remains unclear – the Intel 10 process is unsuitable for taking micrographs of cores “on the knee”, at home it is not easy to polish silicon without severe damage to make the structure clear – although 16 similar sections, but it is possible that 1-2 of them do not contain the x86 core, but the memory controller logic) plus processor and chipset interfaces (PCIe, DDR including the controller, etc.). Intel tiles are therefore significantly larger than AMD chipsets.

So even though it is not a monolith, the cores are large. For comparison: The first generation Epyc modules measured 212 mm² each and the Epyc carried (up to) four. Current chiplets (Zen 3) measures 81 mm², the processor carries up to eight and one central 12nm chiplet of 416 mm² (Epyc Milan = 1062 mm² of silicon). Each module Sapphire Rapids measures about 400 mm², so all four together = 1600 mm² of silicon. A half-higher area would certainly not be a problem in itself. However, we must not forget that the yield of the 400 mm² Intel bit will be different from the 81 mm² bit of the AMD. Furthermore, the AMD processor contains only one such large chiplet and it is also produced on a very mature (and cheap) process, not on the latest top Intel. Thus, although it is not a monolith, the recovery requirements remain incomparably higher than those of AMD.

But that’s not the end of it. From the processor case image Sapphire Rapids (above), which is not yet equipped with silicon, lighter rectangular fields are well visible in place of adjacent tiles. The tiles are interconnected with the help of bridges. Each two interfaces with one EMIB bridge, ie. 10 bridges used to connect four tiles (not counting the other four for connecting HBM, as HBM will cover the next half generation Sapphire Rapids). Although the bridges allow the interconnection of chipsets with higher data throughput than the conventional substrate routing used by AMD in the current generation. However, the question is whether this higher data throughput is worth the complications that can lead to the real fact that the processor (which should have been on the market for a year) will still be in the laboratories for almost three quarters. For the sake of completeness, it is worth mentioning that in addition to the silicon on the four basic tiles and the ten silicon bridges connecting these tiles, the case is integrated by another small silicon chip in the form of an FPGA.

Intel Sapphire Rapids (56 jader Golden Cove)
↓ components ↓areapiecestotal
tile [Intel 7]400 mm²1600 mm²
EMIB10,6 mm²10×106,3 mm²
FPGA30,6 mm²30,6 mm²
total silicon:1737 mm²
AMD Milan (64 years old Zen 3)
↓ components ↓areapiecestotal
chip (x86) [TSMC 7nm]80,7 mm²645,6 mm²
čiplet (IO) [GF 12nm]416 mm²416mm²
total silicon:1062 mm²

Of course, the situation can be viewed differently. Some may like the AMD solution, which went the way of chipsets, but chose the implementation of maximizing benefits while minimizing costs (small chipsets on a new process, bigger only on older cheap ones; a concept based on available technologies without the need for exotic interconnects). This approach can be classified in the so-called “KIS” or Keep It Simple, which can be briefly described as “every element that is not necessary to achieve the goal is undesirable in the design, because it can bring a problem”. Some, in turn, may like Intel’s approach, which obviously uses a combination of more complex but technologically interesting solutions that are currently causing problems, but which over time can bring Intel a wider range of options in developing new products. However, from a market perspective, AMD’s approach, which is innovative but only to the extent that it brings practical benefits, is currently winning.

Source: by

*The article has been translated based on the content of by If there is any problem regarding the content, copyright, please leave a report below the article. We will try to process as quickly as possible to protect the rights of the author. Thank you very much!

*We just want readers to access information more quickly and easily with other multilingual content, instead of information only available in a certain language.

*We always respect the copyright of the content of the author and always include the original link of the source article.If the author disagrees, just leave the report below the article, the article will be edited or deleted at the request of the author. Thanks very much! Best regards!