Intel boasted Xeony Sapphire Rapids and Xe-HPC

Let’s start with the accelerator Old Bridge, Xe HPC. Intel has revealed some parameters on a pair of very similar slides (below), which differ in part in that the former lists the numbers valid for a particular tile and the latter the numbers for the entire accelerator. For example, if the specifications specify 4 MB L1 cache per tile (slide on the left) and the entire Xe HPC carries 16 compute tiles, this means a total of 64 MB L1 cache (right).

It’s a little less clear how Intel got a total of 408 MB L2 cache from the 144 MB L2 cache on the tile (if you have an idea, feel free to brag about the discussion – I admit I didn’t figure it out).

However, Intel still keeps more detailed specifications under wraps, so unit numbers, beats, or performance data are still missing from our table.

AMD
Instinct
MI250X
Intel
Vehicle-HPC
Nvidia A100
GPUAldebaranOld BridgeGA100
architectureCDNA 2CarAmpere
formatOAMOAMSXM4
CU / SM220
(256)
128108
FP32 jader14080
(16384)
?6912
FP64 jader?3456
INT32 jader?6912
You have. Colors880?432
rate≤1700 MHz?1410 MHz
↓↓↓ T(FL)OPS ↓↓↓
FP16
383?78
BF16
383?39
FP32
95,7
47,9
?19,5
FP64
47,9~37 ?9,7
INT4
383??
INT8383??
INT16???
INT32??19,5
FP16 tensor383?312/624*
BF16 tensor383?312/624*
FP32 tensor95,7
?19,5
TF32 tensor
?156/312*
FP64 tensor
95,7?19,5
INT4 tensor?1248/2496*
INT8 tensor
383?624/1248*
↑↑↑ T(FL)OPS ↑↑↑
TMU?432
LLC16 MB408 MB40 MB
bus8192bit8192bit?5120bit
capacity
memoirs
128 GB128 GB?80 GB
HBM23,2 GHzHBM2E3,20 GHz
memory.
permeable
3277 GB/s?2048 GB/s
TDP500W
560W
~615W?400 W
≤600 W
transistorů58.2 billion100 billion54.2 billion
GPU area??826 mm²
process6 nm
Intel 7
7nm, 5nm
7 nm
date202120222020

However, based on figures reported by Intel about the entire Aurora supercomputer, the Anandtech editorial team derived the approximate power of 37 FP64 TFLOPS per accelerator at about 615 watts from the number of processors and accelerators used.

The individual Xe-HPC tiles are manufactured on three different processes: Intel 7 and two TSMC processes: 7nm and 5nm. In contrast, AMD uses 6nm (ie essentially 7nm with EUV) on the newly released Instinct MI250X.

Let’s move on to the Xeons. To get the press in the mood, Intel first came up with a chart comparing Xeon performance with AMD’s Epycy. Some editors were so dazed by the high numbers of Xeons that they presented this slide as Xeon results. Sapphire Rapids – in reality, however, it is the current (third) generation, ie Xeons Ice Lake:

So the generation that in the first independent tests barely managed to compete with the Epyci with the Zen 2 core, and which in our test turned out that the sixteen Ice Lake cores are on average at the level of the 16-core Threadripper X1950:

Therefore, it cannot be blamed for these editors that these superlatives and tens of percent values ​​exceed the 64-core Zen 3 did not connect with Ice Lake, which has real problems with 32 – core models, and considered them a presentation of the next generation.

Now to the future generation – Sapphire Rapids. Intel has released a nice scheme of this Xeon, which carries four processor tiles and four HBM2e chips with a total capacity of 64 GB. But as we already know, the first generation Sapphire Rapids HBM will not be equipped with memories and will rely on a combination of cache with traditional memory modules; HBM release is expected later. Both versions will differ in the dimensions of the case – the classic has 78 × 57 mm, with HBM 100 × 57 mm. The housing of the classic version integrates 10 jumpers (EMIB), the housing of the version with HBM a total of 14.

Intel continues to present Xeon in a public roadmap Sapphire Rapids with HBM as a product of 2022. In the middle of this year, the leaked official roadmap, however, stated a six-month interval between the two versions, and given that so far everything indicates the real availability of Xeons Sapphire Rapids (without HBM) in the middle of 2022, models with HBM from 2022 probably won’t make much, if at all.


Source: Diit.cz by diit.cz.

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