Infinity Cache for APU? AMD is probably planning something better

The editors of the VideoCardz website pointed out the code according to which the third graphics chip of the RDNA 2 architecture would Navi 23, should carry 32 MB of Infinity Cache. It will therefore be significantly less than at Navi 22 (Radeon RX 6700 XT) a Navi 21 (Radeon RX 6900 XT / 6800 [XT]), however, this core targets a lower performance segment and the bus width is half that of the top model (Radeon RX 6900 XT), so there will be no need to compensate for such a significant deficit in gross memory throughput.

We also learn that “small” APUs Van Gogh (for which Microsoft was supposed to have exclusivity, but which canceled or postponed some products) will not be equipped with Infinity Cache.

HELP Van Gogh will support very fast LPDDR5 (these are available in the LPDDR5-5500 version and are also being prepared by LPDDR5-6400). There were reports of even a 256bit bus, which was based on a real background, but it was probably a false detection / recalculation and the reality will be rather 128bit (4 channels, but 32bit). However, which is still very much for 9W APU ratios, it means data throughput of 88 GB / s for LPDDR5-5500 and 102.4 GB / s for LPDDR5-6400. For comparison: the current mobile 35W APU Cezanne has a data throughput of 51.2 GB / s with two-channel connection of classic DDR4-3200. 9W Van Gogh with practically twice as much, he doesn’t need Infinity Cache (so somehow I think half would be enough for him, but that would be a topic for another article).

Infinity Cache in Navi 21

However, according to leak Bondrew, AMD is preparing a larger cache for future APUs, but it will not only be an Infinity Cache, but also an SLC. We could meet the abbreviation SLC already in the context of the SoC Apple M1, but it would be necessary to point out that this is not the first product with this solution – rather the first product on which it was marked with the abbreviation SLC.

This acronym may seem a bit unfortunate, as it evokes the meaning of Single-Level Cell used in the context of Flash memory. However, in the case of SoC / APU, it means something else. SLC stands for System Level Cache and refers to the top-level cache to which all (or at least all significant) SoC / APU components have access. In our context, therefore, both the GPU and the CPU.

For example, Intel has already used SLC (last-level cache accessible to both processor and graphics cores) on some of its integrated graphics processors. However, it cannot be said that its implementation would bring any competitive advantage, APU AMD surpassed this solution even without it. The problem probably lay in the fact that neither Intel’s processor nor graphics cores were so powerful that the standard bus limited them significantly, so that the top-level common cache had a negligible impact (more precisely, it did not represent a competitive advantage).

In the case of the Apple M1, we don’t know much about SLC. Apple does not provide any further details in the publicly available specifications, and there is also a debate about what capacity it actually achieves. The editorial staff of the Arstechnica website is of the opinion that it is 8MB, the editorial staff of the Anandtech website believes that it is 16MB. In any case, it can be said that according to the measurements of Anandtech conceived by the processor cores, SLC in most situations does not have a significant impact on data transmissions and is manifested rather in specific cases. It seems that the SLC M1 will mainly serve the integrated GPU, which has almost 2 times higher performance than the current iGPU in the x86 PC world, or other integrated circuits.

We expect that in the case of future AMD APUs, Infinity Cache will not be implemented in the sense of separate graphics chips, ie only for the needs of the graphics core, but it will be a full-fledged SLC, ie the last level cache available to graphics and processor cores. As the official chart shows, AMD also tested capacities such as 8 MB, 12 MB and 16 MB, which can be used in the APU segment.

physical
permeable
IC
area
IC***
hit-rate and effective IC throughput (GB / s)
1920×10802560×14403840×2160
8 MB124 GB/s8 mm²25 %3117 %2114 %17
12 MB186 GB/s12 mm²31 %5819 %3515 %28
16 MB248 GB/s16 mm²37 %9225 %6217 %42
24 MB373 GB/s24 mm²48 %17931 %11624 %90
32 MB497 GB/s32 mm²55 %27339 %19426 %129
48 MB745 GB/s48 mm²66 %49249 %36534 %253
64 MB993 GB/s64 mm²72 %71559 %58641 %407
96 MB1490 GB/s96 mm²78 %116266 %98352 %775
128MB1987 GB/s128 mm²81 %160974 %147062 %1232

The table shows the approximate conversion of the graph (ie the situation in terms of the graphics core) into numerical values. It tells us that in 1920 × 1080 resolution it would:

  • 16MB Infinity Cache would increase the effective throughput by ~ 92 GB / s in 1920 × 1080 resolution (with the current two-channel DDR4-3200, which reaches 51.2 GB / s, it would be a 180% increase)
  • 12 MB Infinity Cache would increase effective throughput by 58 GB / s (ie by 113%)
  • 8MB Infinity Cache o 31 GB/s (tj. o 61 %).

In the case of use as an SLC cache, where the processor cores would occupy something, of course, the increase could be a bit lower. However, AMD will certainly be able to somehow balance the use of this cache with respect to primarily graphics and primarily processor load.


Source: Diit.cz by diit.cz.

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