Hynix showed the 24 GB HBM3-6400 at the OCP Summit

HBM3 has been waiting a long time. Samsung announced them for the first time in 2016 at the turn of 2019/2020. But with the fall in the price of memory and a reduction in revenue, the manufacturers then decided to turn HBM into a high-end, whose prices will not fall and which will be profitable only to the most expensive systems. There was an intention to issue so-called low-cost HBM (LC-HBM, in the table below) for common equipment, there was a motivation for a fast cadence of new generations, which would push prices down. And so, instead of the turn of 2019/2020, HBM3 could be seen by the public for the first time two years later, now at the OCP Summit, where Hynix exhibited a real chip.

The positive news is that in the first half of the year, the company talked about a 5.2 Gb / s interface, which would reach a transfer rate of 666 GB / s, ie less than the then expected standard of 6.4 Gb / s. Shortly afterwards, Rambus announced that it can license an interface that handles up to 8.4 Gb / s, and now Hynix is ‚Äč‚Äčintroducing significantly faster 6.4 Gb / s chips. There is no point in looking for conspiracy theories, Hynix was already listed as one of its customers in the marketing graphics of Rambus (above).

HBMHBM2LC-HBMHBM2EHBM3
HynixRambus
bus1024bit1024bit512bit1024bit1024bit
interface speed1 Gb/s2 Gb/s~3 Gb/s3,6 Gb/s6,4 Gb/s8,4 Gb/s
give. permeability128 GB/s256 GB/s~200 GB/s461 GB/s819 GB/s1075 GB/s

On the chip, in addition to reaching (in terms of the expected standard) a full 6.4 Gb / s and therefore a transfer rate of 819 GB / s, there is an interesting capacity of 24 GB. The chip consists of twelve data layers, so each has a capacity of 2 GB (16 Gb). While in the HBM and LPDDR segments, practical “one and a half times” the usual capacities are slowly but surely spreading, in the GDDR segment, where this option would be more appropriate (if 8 GB becomes tight in the higher mainstream and 16 GB still seems unnecessary, it would be equipped with 12 GB even on the 128 / 256bit bus, etc.), after this option there is neither sight nor hearing yet.

Finally, we can stop at why we are talking about the expected standard. JEDEC has not yet issued the HBM3 standard. When the so-called HBM2E, originally unplanned, was consecrated, expert opinions emerged that this was a de facto extension of the HBM2E era, so we would still wait for HBM3, which happened. Nevertheless, it is quite curious that we have been seeing a memory product that has been in the pipeline for years – and is already real – we expect the hardware to be equipped with it within a year, but there is still no standard to define this memory product.


Source: Diit.cz by diit.cz.

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