What does DDR5 give us? What DDR4 does is only in a faster format.
What does DDR5 hold?
Even today, most PCs are rumbling with DDR4 memory, but the next-generation standard, which is not surprisingly called DDR5, is already knocking on the door. If we want to simplify it a lot, the goal of new solutions for development is always the same: to increase performance while keeping consumption within reasonable limits. Whatever memory standard we take as an example, this goal has always been met to a roughly similar extent.
Nor can we talk about a different lineup with DDR5, as this system also focuses on increasing performance compared to DDR4 while keeping power consumption at the usual level. If we focus on the raw data, the main changes are that the operating voltage decreases from 1.2 V to 1.1 V, and the 8n prefetch buffer is replaced by 16n prefetch, ie 16 bits per clock are transferred from the memory cells to the IO. buffer as the power will scale from 3.2 Gbps to 6.4 Gbps per I / O connection. Of course, higher performance may be available, as the original JEDEC specifications for DDR4 have been exceeded by some memory vendors, and DDR5 does not miss this option, but the standardization body still covers this range.
The design of DDR5 memory modules, like the DDR4 options, is based on 288 needles, but of course the two solutions are not compatible, meaning that a platform designed to use DDR5 is required. Just because a lot of things change under the hood. Among other things, a DIMM itself will be divided into two channels. Thus, instead of the previous one, a 64-bit channel, a memory module offers two 32-bit channels, of which 40 will be 40 bits in addition to ECC.
The minimum stroke length also varies, specifically from 8 bytes to 16 bytes, which means that a channel can already receive 64 bytes of data per operation, and since a module works with two channels, this means 64 bytes twice. However, these channels are not as wide as before, so the DDR5 standard increases the number of banking groups from four to eight, but more importantly, it treats them with a fine-grained update that allows each memory bank to be updated even if the others are currently working. This allows unused banks to be used sooner, maximizing the availability of less wide channels.
The above are useful changes, but not enough to double the performance compared to DDR4 – you need to increase the clock on the memory bus, which DDR5 does using DFE, or decision feedback equalization. In practice, this modified the memory bus of DDR4, which made it possible to reduce interference, all of which provided a good basis for achieving higher data rates with adequate stability.
Regarding voltage regulation, JEDEC has also introduced a major innovation. Starting with the DDR5 standard, each memory module is responsible for its own voltage regulation, so this load is removed from the shoulders of the motherboards. This is important because motherboards have always had to design for the maximum possible memory configuration when designing motherboards, while in many cases the memory package purchased did not even come close to what the system was theoretically prepared for, making it more expensive to manufacture more modern motherboards.
Of course, it can be immediately shouted that the new specifications will increase the cost of building memory modules, but it is not a negligible factor that the power supply of the system will become realistically predictable. It is now enough to put a controller on a memory module that is just enough for stable operation, eliminating the basically wasteful over-design. However, it may be useful to know that starting with DDR5, it has become pointless to buy expensive motherboards designed for memory tuning, as increasing the memory clock will depend solely on the capabilities of the module and CPU memory controller. Of course, there will be no need to fear the motherboard manufacturers, this little problem will surely be bridged by the miraculous power of marketing.
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Source: Hírek és cikkek – PROHARDVER! by prohardver.hu.
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