Emerald Rapids Xeons increase L3 cache by 2.7x and tell about Intel’s problems

Sapphire Rapids in a nutshell

Currently released Xeons Sapphire Rapids they were a very long, difficult and complicated birth. It was Intel’s first tiled solution for servers, which it committed after a long-continued (and essentially futile) attempt to produce large processors as monoliths. The problem was that Intel didn’t make things too easy by tiling, because it chose an extremely complex way to connect them together, with the individual tiles themselves not being significantly smaller than the original monoliths. Older revisions Sapphire Rapids had a tile area close to 400 mm², the newer one reduced it to 377.5 mm². All Xeon Ice Lake it carried 628 mm² of silicon, so the area of ​​the monolithic component did not even halve.

Sapphire Rapids tiles

Let us recall that Sapphire Rapids consists of four identically equipped tiles. Each physically carries 15 processor cores. Originally, a configuration with at most 56 active cores (ie one would be disabled in each tile) was supposed to go on the market, but considering the (multi)generational performance slippage, Intel finally launched at least one model with a full 60 cores. The individual tiles are identical in terms of equipment and design, only they are optically inverted to make it easier to take them down and connect them. EMIBs (connecting bridges) are used for this purpose Sapphire Rapids it needs a total of 10 (despite Intel’s simplistic graphics painting four).

Emerald Rapids

Emerald Rapids was understood from the beginning as Sapphire Rapids-refresh. The same architecture with a ~10% higher number of cores, optimizations and increased cache does not leave room for any significant shift in performance, and therefore it cannot be expected that this series could significantly improve Intel’s competitive position.

source: SemiAnalysis

But now it turns out that (despite the number of cores and the expected competitiveness) it is Emerald Rapids quite a significant change in terms of design. No, nothing changes on the architecture of the x86 cores, but quite a lot changes around. Let’s start with what is closest to the core and the cache. L3 cache u Sapphire Rapids was 1920kB for each core. Emerald Rapids will increase the capacity to 5120 kB, i.e. 2.67x. Furthermore, the structure of the processor is significantly reduced. It will no longer be 4 tiles with an area of ​​377.5 mm² each, but only(!) 2 tiles with an area of ​​746.5 mm² each. This means that the tiles will increase very significantly, above the level of a monolithic Xeon Ice Lake (628 mm²) and monolithic Xeon Skylake (694 mm²).

source: SemiAnalysis

It follows that after experience Sapphire Rapids sees Intel as more feasible to go back to large pieces of silicon (>600mm²) than to tackle a fast but apparently extremely demanding multi-tile interconnect via high number of bridges (EMIB) system.

Left 33j. Emerald Rapids tile (Semi Analysis), right last year presented 34j. silicon (Angstronomics)

Each (of both) tiles carries 33 cores, which means 66 cores for the entire processor, which accounts for 32 active cores per tile and 64 processor cores in total. The 33-core figure is strikingly reminiscent of the 34-core silicon that Intel showed off last fall (it was still unclear what Intel meant by that). It now looks like it may have been one of the configurations under consideration, with development continuing into the 33-core tile.

However, the tiles differ not only in the number of cores. The 34-core configuration carried 1920kB of cache (per core) as Sapphire Rapids, but on the other hand, it was equipped with double DDR5 channels. The 33-core configuration carries 5120kB cache, but has half the DDR5 channels. The larger cache apparently compensates for the narrower memory interface. It could thus be about optimizing the price of the platform.

Emerald Rapids tilessilicon from autumn 2022
L3 cache na j.5120 kB1920 kB
DDR5 interface (160bit)2× (4 channels)4× (8 channels)
PCIe ×16
EMIB PHYagainprobably not

The essential difference is that the silicon from the wafer presented last year lacks anything that would clearly resemble an EMIB interface, so it could be either a test chip or a variant intended for a system with a lower number of cores.

Source: Diit.cz by diit.cz.

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