Processor development has accelerated in recent years. It started with AMD’s motivation not to go bankrupt and return to the large processor segment. This continued with the search for alternative ways to increase performance as new processes help less and less with frequency, consumption and cost reduction. At present, this has resulted in Intel’s efforts not to lag behind and to find a way within current technological means to tighten (and subsequently surpass) AMD’s offer with a combination of large and small cores.
Staying with AMD has brought about a significant change with each passing generation. Zen (outside the new architecture) was modular, Zen 2 brought chiplets, Zen 3 significantly increased IPC, reworked L3 cache and prepared interface for V-cache. From Zen 4 We expect (in addition to the support of new interfaces) a further significant increase in IPC and an expansion of the number of supported chiplets, which will mainly affect servers. As you may have noticed, no generation mentions the production process, as it is used in some, but all of these changes are due to the fact that they alone are far from sufficient to ensure the usual intergenerational shifts in performance.
Other views are a bit foggy. In connection with Zen 4 we can mention the planned update of supported interfaces (DDR5, PCIe 5.0) or the addition of smaller integrated graphics to “stand-alone” processors. As for APUs (where they will make more sense in tandem with integrated DDR5 graphics than with stand-alone processors), the so-called SLC (System Level Cache, a kind of Infinity Cache shared for graphics and processor cores) is expected. However, it is not clear whether in connection with Zen 4 or Zen 5.
Zen 5 CPU – Granite Ridge
Just about Zen 5 new data is now coming. Large (“stand-alone”) processors built on it, which will bear the label Granite Ridge, will combine the 3nm TSMC process on which the processor chiplets will be created with the 6nm TSMC process on which the central (communication) chiplet will be built.
Zen 5 APU – Strix Point
As regards Zen 5 APUs to be named Strix Point, we already know that they will be equipped with “smaller” cores based on Zen 4which was until recently called Zen 4D, but AMD is (perhaps not to be confused Zen 3D) reported under the name Zen 4c. These cores are supposed to have a redesigned cache structure and other modifications, as a result of which they will achieve a more advantageous ratio of the number of cores per unit area and consumption / performance.
From AMD labs
Quite surprising is the information that Strix Point to be made on a combination of 3nm and 5nm process. So it is probably a chip, layered or otherwise folded solution. What will be produced by what process is not known and there are so many hypothetical combinations that one cannot simply say that one is significantly more likely than the other. 3nm can be a processor part, 5nm graphics with a chipset part. It can be the same Zen 5 with graphics on 3nm silicon and core Zen 4c separately at 5nm (for which it was designed). Or 3nm silicon with processor cores and graphics is layered on 5nm silicon with chipset part and SLC (such a variant would be especially interesting). Various other combinations are possible, so take the list only as an illustration of a few variants that make sense for some reason.
There is no specification of the release date yet, but we can start from a combination of different clues. Firstly, we know that APUs are published plus or minus regularly at CES (ie the introduction of a new version of the mobile version every January). Now in January 2022 is expected 6nm Rembrandt (Zen 3+ a RDNA 2) should logically follow in January 2023 Phoenix (Zen 4 + RDNA 2) and then logically published in January 2024 Strix Point (Zen 5 + Zen 4c + RDNA ?). That would indicate a generation Zen 5 is referred to as the Ryzen 8000, in other words that between Zen 4 a Zen 5 no half-generation is created.
In such a scenario, Zen 5 had to go to the market sometime in late 2023, that is, a year after Zen 4. This is a relatively short interval. However, if AMD did not catch it (and Intel released as expected), it would find itself in a very problematic situation (in 2023, Intel is expected to release up to two architectures with a rapid increase in IPC).
Source: Diit.cz by diit.cz.
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