Arguments that semiconductor components should become cheaper with the transition to a “thinner” process technology do not take into account the current realities of the industry, which indicate an increase in manufacturers’ costs as the size of transistors on a chip decreases. Specifically, TSMC will charge customers about $20,000 per wafer for 3nm technology versus $16,000 for 5nm technology.
The resource traditionally shared similar calculations. DigiTimesand detailed information on this topic was published by representatives Tom’s Hardware. According to unofficial sources, the increase in the cost of one 300 mm silicon wafer with 3 nm chips to $20,000 will be due to an increase in the number of layers processed using EUV lithography. Already within the framework of 5-nm technology, the number of such layers can reach 14 pieces, and with the transition to 3-nm technology, it will only grow. For TSMC, this will mean an increase in the need for EUV scanners, which cost at least $150 million each. EUV lithography products also have a fairly long production cycle, and in terms of capital turnover, this also increases the costs of the manufacturer.
All of this implies that TSMC will be forced to pass on rising costs to customers’ wallets, and 3nm products per wafer will be more expensive. One of the first TSMC customers to receive 3nm chips could very well be Apple. It feels the need to reduce the size of transistors and increase the density of their placement, while it is ready to purchase chips in large quantities. Such a scheme of cooperation is beneficial to both parties, it cannot be ruled out that Apple, as the largest client of TSMC, will be able to count on some price concessions. For comparison, in 2018, one wafer with 7nm products was estimated at $10,000, and in 2004, a wafer with 90nm components cost TSMC customers no more than $2,000. A noticeable increase in the cost of chips has been observed since the middle of the last decade, when the main contract manufacturers switched to the so-called FinFET transistor structure, which increased the complexity of the process and the cost of processing silicon wafers.
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