Unlike the first prototypes and most of AMD’s slides, the cache chip is indistinguishable from the rest of the circuit, with a single prong cover at the top.
AMD has launched the first 3D V-Cache processors this spring. The company has presented its stackable cache architecture in several slides, but now the implementation has also been taken a closer look at in practice.
It took almost a year for 3D V-Cach to make its debut before the processors finally hit the market. The implementation of the processors themselves and the stackable cache chip has also changed quite a bit along the way.
When CEO Lisa Su introduced the prototype processor for the first time with the 3D V-Cache, the cache chip was clearly distinguishable from the processor and the filler. According to AMD’s slides, there was nothing special about it, as the structure matched the description of the slides, even though they had at least two types of silicon “shims” around the cache chip. An exception to this is one particular slide shown in the ISSCC, which also has a layer of silicon on top of the cache chip to support the structure.
Tom Wassick, who works with semiconductor packaging technologies, has got his hands on the Epyc 7473X processor, aka Epycin 3D V-Cache, codenamed Milan-X. Wassick quickly elevated the processor and figured out what the actual structure of the final processors is. It was clear from the boom that the description of the ISSCC slide was correct, the previous AMD slides were not; there is another layer of silicon on top of the cache chip to support the structure. Wassick plans to continue cutting the processor to find out more about the chip structure under the “cover”. As you can see from the pictures, after figuring out the structure of the packaging, it is no longer unnecessary to wait for a playing game from Wassick’s Milan X processor.
Source: io-tech.fi by www.io-tech.fi.
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